As with process technologies used to make logic chips, DRAM ICs need the usage of EUV lithography as transistors get smaller. Nowadays, Samsung and SK hynix use EUV for a few layers, which is expensive. To make EUV considerably cheaper, DRAM makers will have to adopt three-dimensional transistors and new DRAM structures, said a researcher from SK hynix at an industry conference, reports The Elec.
DRAM makers constantly strive to make their memory cells as small as possible and make their ICs as small as likely to be more competitive. To do so, they usually adopt new process technologies and, once or so, adopt new DRAM cell structures (once a decade or so). Today’s DRAMs use 6F^2 (6F2) cell design, for example, which has been using FinFET three-dimensional transistors for over a decade; DRAM has been using plain transistors mainly because each new process node introduced new ways to shrink DRAM cells, which was all memory makers needed.
But preserving the 6F^2 cells and plain transistors with EUV does not seem as fruitful as once thought, according to SK hynix researcher Seo Jae Wook, who spoke at an industry event. He says that with vertical channel transistors (VCTs), or 3D DRAM, ‘the process can be designed to reduce the cost of EUV processes by half.’
Meanwhile, The Elec says that SK hynix is gearing up to wed VCT and 4F^2 (4F2) cell design to make ultra-dense DRAMs (arguably, a risky but ambitious move). However, the memory maker has not confirmed such plans publicly. Therefore, when SK hynix starts to use EUV more extensively several years later, it will have experience both with VCTs (e.g., FinFET or even gate-all-around transistors) and with 4F^2 cell structures. The latter promises to reduce DRAM density by 30% compared to 6F^2 at the same node.
Fab tool maker Tokyo Electron anticipates that DRAMs using vertical channel transistors (VCTs) and a 4F^2 cell design will begin to appear around 2027 to 2028. The company also expects that to produce these VCT-based DRAMs, memory manufacturers will need to adopt new materials for capacitors and bitlines.
SK hynix and Samsung reportedly aim to apply 4F^2 cell design with their sub-10nm process technologies, though details are scarce. Samsung’s first-generation sub-10nm DRAM fabrication process is still two generations away. Currently, Samsung’s most advanced DRAM production node is its 5th Generation 10nm-class (12nm) technology, which it began to use in mid-2023. According to a slide leaked earlier this year, Samsung plans to develop two more 10nm-class fabrication processes before introducing the first-generation sub-10nm node, which is expected to debut in the decade’s second half.
In addition to using EUV, 4F^2 cell design, and VCT transistors, Samsung plans to implement stacked DRAM process technology in the early 2030s, which will further boost the density of its memory devices over the next decade.
