TSMC started to produce chips on its performance-enhanced N3P (3rd Generation 3nm-class) process technology in the fourth quarter of 2024, as planned, the company revealed at its North American Technology Symposium 2025. N3P succeeds N3E and targets client and data center applications that require enhanced performance while retaining 3nm-class IP. The technology will be succeeded by N3X in the second half of this year.
TSMC’s N3P is an optical shrink of N3E that retains design rules and IP compatibility while offering 5% higher performance at the same leakage or 5% – 10% lower power at identical frequencies, along with a 4% transistor density boost for designs with a typical mix of logic, SRAM, and analog blocks. As N3P’s density gain comes from improved optics, it enables better scaling across all chip structures, particularly benefiting SRAM-heavy high-performance designs. N3P is now in production — so the company is currently building up products on this technology for its lead customers.
Advertised PPA Improvements of TSMC’s New Process Technologies
| Row 0 – Cell 0 |
N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
|
Power |
-25% ~ -30% |
-34% |
-5% ~ -10% |
-7%*** |
|
Performance |
10% – 15% |
18% |
5% |
5%, Fmax @1.2V** |
|
Density* |
? |
1.3x |
1.04x |
1.10x*** |
|
Hvm |
Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
*Chip density published by TSMC reflects ‘mixed’ chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
But the era of 3nm-class process technologies for high-performance applications does not stop at N3P. The node will be followed by N3X, which promises to increase maximum performance by 5% at the same power or reduce power consumption at the same frequency by 7% when compared to N3P. However, the key benefit of N3X compared to N3P is its support for up to 1.2V voltage (which is extreme for a 3nm-class technology) which will enable the absolute maximum frequency possible (Fmax) for applications that need it (i.e., client CPUs). That Fmax comes with a tradeoff: up to 250% higher leakage power — so chip developers must be careful when building N3X-based designs that feature a 1.2V voltage. Mass production of N3X chips is on track for the second half of this year.
“ N3P started production late last year, in 2024,” said Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC. “We continue to enhance our 3nm technology. […] Our strategy has been after our introduction of the new nodes, we continue to do enhancement in order to allow our customer to harvest the technology scaling benefit. […] We recognize it is a significant investment for our customers to get [to a new] node, for example, developing IP on the ecosystem. So, we want our customer continue to harvest more benefits from their investment at each new node, but at the same times we are providing them enhancement at a product level.”
TSMC tends to offer multiple iterations of process technologies within one process development kit (e.g., N5, N5P, N4, N4P, N4C). On one hand, this allows the company to use expensive equipment for as long as possible — on the other hand, this also allows its customers to reuse their IP for as long as possible. Therefore, N3P are N3X are natural additions to the N3 family of production nodes.
While the eyes of technology enthusiasts are on TSMC’s 2nm-class fabrication processes that rely on gate-all-around (GAA) nanosheet transistors, the vast majority of advanced processors for client applications that will hit the market in the coming quarters (including the next-generation of iPhones, iPads, and Macs) will be made on TSMC’s N3 family of process technologies.
