TSMC on Thursday reported its strongest quarter ever, posting a revenue of $30 billion for the second quarter of 2025, citing strong demand for AI processors. The foundry expects demand for AI applications to grow in the coming years, so it is plotting a rather unprecedented expansion plan that involves building 15 new fabs over the course of the next several years.
$30.07 billion in Q2: Best quarter ever
For the second quarter of 2025, TSMC posted $30.07 billion in revenue (NT$933.79 billion), marking a 38.6% increase compared to the same period last year and a 17.8% rise from the previous quarter. The foundry’s net income stood at $12.825 billion (NT$398.27 billion), up 60.7% year-on-year, while earnings per share came in at NT$15.36, or US$2.47 per American Depositary Receipt. TSMC’s gross margin hit 58.6%, which is an unprecedented result for a contract chipmaker that does not sell chips under its own brand.
Advanced process technologies (7nm-class and thinner) continued to dominate wafer revenue, with 3nm-class production node contributing 24%, 5nm-class accounting for 36%, and 7nm-class standing at 14%. Altogether, technologies these processes represented 74% of the total. As for applications, HPC commanded 60% of TSMC’s wafer revenue, smartphones accounted 27% of sales, whereas automotive and IoT contributed 5% each.
TSMC’s HPC platform is a rather vague classification, which includes everything from low-end CPUs for client PCs to system-on-chips for game consoles and from high-end CPUs to monstrous AI processors using advanced packaging. This time around TSMC specifically noted that high demand from AI and HPC clients remained a key factor in the quarter’s performance.
Expansion plan
Processors for AI applications tend to be big and will get bigger in the coming years, consuming more silicon than ever. A good example of such development are Nvidia’s Rubin Ultra accelerators that will use four reticle-sized compute chiplets in 2027, increasing demand for TSMC silicon by at least two times.
Today, demand for TSMC’s N5 (5nm/4nm-class) and N3 (3nm-class) fabrication processes is so strong that the company can barely meet it, even despite the fact that all of AMD’s and Nvidia’s AI GPUs are made using proven 4nm-class production nodes (N5P, 4N, 4NP) and only the latest AMD’s Instinct 355X uses TSMC’s N3 node. That said, it is not surprising that to meet demand for advanced AI GPUs in the coming years, TSMC must expand its manufacturing capacities. Apparently, this is what the company plans to do.
TSMC’s current plan for the ‘next several years’ includes building 11 new fabs and four advanced packaging facilities in Taiwan alone. If we add overseas fabs on different stages of development (one in Japan, one in Germany, two or three in the U.S., depending how you count), this means that the company is on track to build 15 or more new fabs ‘over the next several years,’ which is a foundry expansion plan that has never been seen before.
“In Taiwan, with support from the Taiwan government, we plan to build 11 wafer manufacturing fabs and four advanced packaging facilities over the next several years,” said C.C. Wei, chief executive and chairman of TSMC, during the quarterly earnings call with analysts and investors. “We are preparing for multiple phases of 2nm fabs in both Hsinchu and Kaohsiung Science Parks to support the strong structural demand from our customers.”
‘Over the next several years’ is vague description of TSMC’s plans, so analysts went on to ask about TSMC’s CapEx in the coming years to find out when to expect these fabs coming online and how much the company intends to spend on its upcoming manufacturing capacities. For example, the company’s CapEx budget for 2025 is between $38 billion and $42 billion and the company has nine production facilities (including semiconductor fabs and advanced packaging facilities) at different stages of readiness in the works. Unfortunately, the only thing that TSMC confirmed at this time is that its CapEx will not suddenly drop in ‘any given year.’
“As long as there are business opportunities, we will not hesitate to invest,” said Wendell Huang, Chief Financial Officer of TSMC. “We also take [macroeconomic uncertainties] into consideration in our capacity and CapEx plan. Going forward, it is too early to talk about future years’ CapEx, but I can share with you [that with] a company of our size, it is unlikely that you see CapEx dollar amount suddenly drop a lot in any given year.”
N2 is ready for HVM in late 2025, but expect capacity constraints
In addition to outlining its expansion plans, TSMC also said that development of its next-generation nodes is on track with mass production of chips using its N2 (2nm-class) process technology set for the second half of this year and high-volume manufacturing of products using its A16 (1.6nm-class) technology is on track for the second half of 2026. The company stressed once again that its A16 node with its Super Power Rail (SPR) backside power delivery network (BSPDN) is aimed primarily at AI and HPC applications with high demands for power and complex power routing.
“N2 is well on track for volume production in the second half of 2025 as scheduled with a ramp profile similar to N3,” said Wei. “[…] A16 is best suited for specific HPC products with complex signal routes and dense power delivery network. Volume production is on track for second half 2026.”
TSMC says that ramp profile of N2 will be similar to that of N3 in 2022 – 2023, which likely means that TSMC expects a limited number of customers or products initially, with volume picking up over several quarters. This mirrors the advance of N3, which began volume production in late 2022, but TSMC only recognized the first N3 revenue in Q3 2023 despite the fact that Apple got its first N3B silicon in April (as N3 cycle time is around four months). However, this time around TSMC says that N2 will make contributions to its revenue starting in the first half of the year.
“We are ramping [N2] in the second half of this year,” said Wendell Huang, chief financial officer of TSMC. “We expect the revenue to come up in the first half of next year.”
We already know from TSMC (and at least from one of its customers) that N2 has been adopted by more customers than N3 and N5 in the first year, so the foundry will be ramping up production for more than one client. Apparently, relatively slow ramp of N2 will be conditioned by capacity constraints. However, the company will be earning more dollars per N2 wafer compared to N3 due to higher quotes.
“N2 ramp is limited by our capability to build a new fab, to ramp it up, and also a little bit straightforward is constrained by the capacity,” Wei said. “So. we say the ramp profile is similar to N3, but the revenue contribution certainly will be bigger because you don’t expect our N2 is the same price as N3, right?”
TSMC still has to disclose how long will its N2 cycle be, but it will barely be shorter than N3’s four months, so expect the company’s customers to get their N2 chips next spring provided that the foundry starts to make 2nm-class chips in December, 2025.
A16 – First leading edge node to be adopted by AI/HPC
One interesting thing to note about TSMC’s A16 is that it will be the company’s first leading-edge node in years aimed at AI/HPC applications and adopted by designers of appropriate processors.
For years, TSMC designed its leading-edge nodes primarily for client applications, such as smartphone processors developed by its alpha customer Apple. As a result, companies like AMD, Intel, and Nvidia hardly ever use the latest fabrication nodes, but stick to previous-generation N+1 or N+2 technologies. By contrast, A16 is designed primarily for AI and HPC processors.
“Our HPC customers are always one step behind using N+1 or N+2 technologies,” Wei said. “[…] When we talk about A16, we have a power efficiency improvement [compared to N2P] close to 20%. That’s a big value for all the AI data center applications. […] So, it is not a surprise for TSMC to expect those people in the AI data center industry […] to use in A16.”
However, those who plan to use A16 with SPR will have to up to $45,000 per wafer, if rumors are correct.
A14 is on track
As for TSMC’s A14 process technology — which relies on the company’s 2nd Generation nanosheet gate-all-around (GAA) transistors and is aimed at client applications, so it does not feature BSPDN — it is still on track for mass production sometimes in 2028 with its successor aimed at HPC (with BSPDN) scheduled for 2029.
“Our A14 technology development is on track and progressing well with device performance and yield improvement on or ahead of schedule,” Wei said. “Volume production is scheduled for 2028. We will continue our strategy of continuous enhancement with A14, including a Super Power Rail offering planned for 2029.”
Summary
TSMC reported record-breaking financial results for the second quarter of 2025, with revenue reaching $30.07 billion, driven largely by demand for AI-related chips.
To meet demand for its production in the coming years, TSMC outlined an unparalleled expansion plan that includes building 15 or more new facilities over the next several years, with 11 fabs and four advanced packaging sites planned in Taiwan alone, alongside ongoing construction in Japan, Germany, and the U.S.
Meanwhile, production ramp for the N2 node is set for late 2025, with revenue contributions expected in the first half of 2026. A16, focused on AI and HPC applications, is on track for mass production in late 2026, followed by A14 in 2028 for client products.
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